1. Field of the Invention
The present invention relates to the field of integrated circuit design, in particular, design of very large scale integration (VLSI) circuits. More specifically, the present invention relates to managing timing requirement specifications and measurements, and generating timing models and constraints for a VLSI circuit.
2. Background
Today, many VLSI circuits including microprocessors are designed using a top down approach. Under the top down approach, a VLSI circuit is specified as an hierarchy of functional block instances. A functional block instance is an instance of a functional block. For examples, register files "reg1" and "reg2" are functional block instances of the register file "reg" functional block. The hierarchy starts with a root block instance and has one or more generation of offspring block instances. The root block instance represents the total aggregation of the functionalities of the VLSI circuit, whereas the different generations of offspring block instances represent varying degrees of decomposition of the various functions of the VLSI circuit. The immediate ancestor of a number of offspring block instances is referred to as the parent block instance of the particular offspring block instances, and the particular offspring block instances are referred to as the child block instances of the particular parent block instance. A functional block instance with no offspring block instance is also referred to as a leaf block instance. A leaf block instance may or may not be at the gate level, depending on the needs of the designers. Additionally, a collection of connected pin instances, typically spanning over a number of functional block instances, is referred to as a net. The functional block instances of a portion of an hierarchical representation of an exemplary microprocessor is illustrated in FIG. 8. A net of the exemplary microprocessor is illustrated in FIG. 9.
The design starts with specifying or budgeting the requirements of the various functional blocks, from top to bottom, including the behavior, power consumption, physical area, and timing requirements of each of the functional block. The requirements specified for a functional block apply to all its instances. As the leaf blocks are designed or implemented with actual circuit elements, attempts are made to measure and confirm that indeed the various requirements of the functional blocks are met for all functional block instances, using a bottom up process. If the specified requirements are not being met, either the design/implementation of the leaf blocks are altered or the specifications are changed reallocating the requirements among the various functional blocks.
In order to be able to specify the timing requirements and subsequently confirm the timing requirements are being met using the above described top down approach and bottom up process, the timing specifications of the various functional blocks and the measurements of the various functional block instances must be stored and compared. Preferably, not only the current timing specifications and measurements are stored, but all historical timing specifications and measurements are stored and maintained.
Traditionally, the timing requirement specifications and measurements are maintained in an ad hoc manner. The timing measurements are taken using a number of commercially available timing analyzers, such as static timing analyzers, SPICE, and synthesis tools. These timing analysis tools are provided with models of the various functional blocks and constraints of the various functional block instances, which are also generated in an ad hoc manner. However, as the complexity of VLSI circuits continue to increase with increasing number of electronic elements, functional blocks and instances, this ad hoc manner of managing timing requirement specifications and measurements for the functional blocks/block instances, and generating timing models and constraints of the functional blocks/block instances, has become increasing inefficient and unacceptable.
Today, it is not uncommon to find a VLSI circuit involving electronic elements in the order of millions, and functional blocks in the order of hundreds. Due to the number of designers involved, it is also not unusual for designers of some of the functional blocks to work in semi-isolation from designers of other functional blocks. Thus, it is desirable to be able to manage the timing requirement specifications and measurements for the functional blocks/block instances, and generate timing models and constraints of the functional blocks/block instances in a systematic manner, allowing timing requirement specification including their confirmation and adjustment to be performed in an efficient manner. As will be disclosed, the present invention provides for such a method and apparatus which advantageously achieves the desired results.